Semiconductor memory devices of flash memory and the like conventionally have been constructed by two-dimensionally integrating memory cells on a surface of a silicon substrate. Although it is necessary to increase the integration of the memory cells to reduce the cost per bit and increase the storage capacity of such a semiconductor memory device, increasing the integration in recent years has become difficult in regard to both cost and technology.
As technology to breakthrough the limitations of increasing the integration, there are methods that three-dimensionally integrate memory cells by stacking. However, in methods that simply stack and pattern one layer at a time, the number of processes undesirably increases as the number of stacks increases; and the costs undesirably increase. Therefore, technology has been proposed to form a stacked body on a silicon substrate by alternately stacking gate electrodes and insulating films; subsequently collectively patterning through-holes in the stacked body; depositing a blocking insulating layer, a charge storage film, and a tunneling insulating film in this order on the side face of the through-hole; and burying a silicon pillar in the interior of the through-hole.
In such a collectively patterned three-dimensionally stacked memory, a charge can be removed from and put into the charge storage layer from the silicon pillar to store information by forming a memory cell transistor at the intersection between each of the gate electrodes and the silicon pillar and by controlling the potentials of each of the gate electrodes and each of the silicon pillars. According to such technology, the through-holes can be made by collectively patterning the stacked body. Therefore, the number of lithography processes does not increase and cost increases can be suppressed even in the case where the number of stacks of the gate electrodes increases.